1. Field of the Invention
The present invention relates to a semiconductor element such as a thin film transistor (hereinafter, referred to as a TFT) and a method for manufacturing a semiconductor device having a circuit including such a semiconductor element. For example, the present invention relates to an electro-optical device typified by a liquid crystal display, an EL (electroluminescense) display device, an EC display device, and the like. The present invention also relates to an electrical unit for improving processing speed formed using a TFT, for example, a central processing unit (CPU), and the manufacturing method thereof. Further, the present invention relates to an electronic device with the electro-optical device and the electrical unit mounted as a part.
2. Description of the Related Art
Recently, the technique for manufacturing a semiconductor element such as a TFT over a substrate has improved drastically and has been developed so as to be applied to an active-matrix display device. Especially, a TFT using a crystalline semiconductor film can operate at high speed since the TFT has a higher field-effect mobility than a TFT using a conventional amorphous semiconductor film.
From a cost standpoint, a glass substrate is more desirable as a substrate used for a semiconductor device than a single-crystal silicon substrate. However, in the case of forming the semiconductor element over the glass substrate, the semiconductor element should be manufactured at such a low temperature that the glass substrate does not melt.
In order to obtain such a crystalline semiconductor film used for the semiconductor element, steps of crystallizing an amorphous semiconductor material or crystallizing an amorphous component included in a semiconductor material to improve crystallinity are required (Reference 1: Japanese Patent Laid-Open No. H11-160734).
In order to obtain such a crystalline semiconductor film, there is a method of conducting a heat treatment after adding a catalytic element promoting crystallization, into an amorphous semiconductor film. However, in the case of using the crystalline semiconductor film obtained by this method, there is a risk of serious deterioration in TFT characteristics due to the catalytic element in the film. Specifically, there is a possibility of increasing off-current in the TFT.
Therefore, the catalytic element in the crystalline semiconductor film needs to be removed (gettered) so as to suppress such deteriorations of the TFT characteristics.
In order to getter a catalytic element, there is a method of using a semiconductor film doped with phosphorus. For example, the catalytic element in the semiconductor film is moved to a part where the concentration of phosphorus is high so as to gettered by conducting a heat treatment after forming a silicon layer anew on a top layer or by conducting a heat treatment after doping a part of a semiconductor film with phosphorus to make a region including phosphorus at a high concentration (Reference 2: Japanese Patent Laid-Open No: H11-97706).
FIGS. 3A to 4B show a conventional process for manufacturing a TFT. First, a gate electrode 1001, a gate insulating film 1002, and an amorphous semiconductor film 1003 are formed over a substrate 1000.
Next, a solution 1004 containing a catalytic element is applied over the amorphous semiconductor film 1003 by a spin coating method (FIG. 3A).
After applying the aqueous solution containing a catalytic element, the amorphous semiconductor film 1003 is crystallized by a first heat treatment to form a crystalline semiconductor film 1005 (FIG. 3B).
Further, a semiconductor film 1006 containing an element selected from Group 15 of the periodic table (typically, phosphorus (P), arsenic (As), or antimony (Sb)) is formed over the crystalline semiconductor film 1005, and then a second heat treatment is conducted. By the second heat treatment, the catalytic element in the crystalline semiconductor film 1005 is moved to the semiconductor film 1006 containing the element selected from Group 15 of the periodic table, that is, the catalytic element is gettered (FIG. 3C).
Next, the crystalline semiconductor film 1005 and the semiconductor film 1006 containing the element selected from Group 15 of the periodic table are patterned to form an island-shaped stacked film (FIG. 3D). A conductive film 1007 is formed to cover the island-shaped stacked film (FIG. 3E). A portion of the conductive film is removed using a mask to form a source electrode and/or a drain electrode 1008 (FIG. 4A).
Subsequently, the semiconductor film 1006 containing the element selected from Group 15 of the periodic table of the island-shaped stacked film is completely removed using the a source electrode and/or drain electrode 1008 as a mask. A portion of the crystalline semiconductor film 1005 is removed to reduce the thickness thereof (FIG. 4B).
Through the above steps, an inversely staggered TFT having source region and/or drain region 1009 and a channel region 1010 is formed.
Conventionally, two steps of heat treatments are needed. In other words, (1) a heat treatment for crystallization, and (2) a heat treatment for gettering a catalytic elementare needed. In a process of manufacturing a semiconductor element, it is preferable that the number of steps is as small as possible since the increase of steps directly leads to increase in cost and decrease in yield.